1. Field of the Invention
The apparatus and method of the present invention generally relates to logic circuits and more particularly to a method of performing a logical NOT function by performing multiple comparisons.
2. Description of the Prior Art
Current methods of analyzing the operation of data processing systems include various methods for extracting data or monitoring the performance of the data processing system while in operation. For example, a software analyzer may be connected to the data processing system in order to monitor accesses to a specific memory location, monitor access to a specific peripheral device, monitor the setting of a specific bit within a memory word, monitor the execution of a program at a specific hardware priority level, or perform a trace of the execution of a software program. The software analyzer functions may be performed during the debugging of the system software, for example, in attempting to determine who is inadvertently destroying data in a specified location, or for system a large bulk of time is being spent, so that that particular section of code may be recoded to execute faster.
Typically, a software analyzer has a recording memory which is used to record events which occur during the execution of software in the data processing system which are of interest to the operator of the software analyzer. This recorded data is then simply printed out to provide a trace of the execution of software or it may be further processed by the software analyzer. For example, the software analyzer may calculate the time difference between the occurrence of a beginning event and an ending event or the number events which occur during a lapsed period of time.
In a typical software analyzer, the operator usually has an ability to select which events will be recorded in the trace memory. This ability to select which events will be traced is important because the tracing of all events may obscure the events of interest. For example, if a software analyzer is being used to determine who is destroying a specific location in memory which is written into with a specific value by many instructions within the program, the software analyzer operator can catch the culprit by specifying that tracing is to occur on all operations that write any value other than the specified (correct) value into the specified memory location. For example, if location 100 in a program initially contains a 0 value, which is frequently replaced by a value of 2 being written into it, but is sometime being inadvertently written into with a value other than 2, the software analyzer operator could request that all software instructions which write into location 100 with a value that is not equal to 2 be traced.
Prior art logic to perform the type of operation described above within a software analyzer is shown in FIG. 1. The logic in FIG. 1 is designed to monitor all memory operations and compare the memory address with the address of interest in address comparator 107 and the memory data with the data of interest in the data comparator 132. Depending upon the output of the address and data comparators, the logic sets or resets trace flop 111 such that trace signal TR+ on line 112 will either indicate that the current memory address and data should be recorded in the trace memory or not recorded.
The logic in FIG. 1 used to generate trace signal IR+ on line 112 operates as follows. Prior, or during the course of execution of the software which is to be analyzed, the trace address register 105, trace condition register 116, trace data register 127 and trace data mask register 130 are loaded with information which is to be used as a trigger point to either initiate or stop the tracing of the software execution. Trace address register 105 is loaded with the address of the memory location whose contents is to be monitored. This memory address may be specified by the software analyzer operator, and at some point in time would be available on lines 104 such that it could be latched into trace address register 105 and be continuously available at the outputs thereof, signals TA+ on lines 106 during the execution of the software. Continuing with the above example, signals on line 104 representing the value of address 100 would be latched into trace address register 105.
Similarly, prior to or during the execution of the software to be analyzed, trace data register 127 is loaded with the data of interest from lines 126 such that the data value will be continuously available at the outputs thereof, signals TD+ on lines 128. In a similar manner, trace data mask register 130 is loaded with a mask value from lines 129 such that the trace data mask will be available as signals TDM+ on lines 131 at the outputs thereof during the execution of the software to be analyzed. Continuing with the above example, trace data register 127 would be initially loaded with a data value of 2 from lines 126 and trace mask register 130 would be initially loaded with an all binary ONE's value such that all bits within the memory word would be analyzed and none of them would be ignored as "don't care" conditions.
Similarly, trace condition register 116 would be loaded either prior to or during the execution of the software. Trace condition register 116 is loaded such that when the address and data value on interest is detected, either the trace flop 111 can be set by initially loaded a binary ONE from line 113 into the set flop such that the output there, signal SE+ on line 117, will be a binary ONE, or it can be conditioned to reset when the address and data is detected by loading a binary ONE from line 114 into the reset flop such that the output thereof, signal RE+ on line 118, will be a binary ONE. In addition, the NOT flop of trace condition register 116 is loaded with the signal which is present on line 115 such that the output thereof, signal NC+ on line 119, will determine whether the setting or resetting specified in the set flop or the reset flop is to occur when the memory data is equal, or when the memory data is not equal.
Continuing the above example, if we wish to trace all memory operations up to the point in time when a value other than 2 is stored into location 100, thereby saving within the trace memory the memory operations which preceded the storing of the non-2 value into location 100, we would set trace condition register 116 such that the output of the set flop (or bit) would be a binary ZERO, the output of the reset flop (or bit) would be a binary ONE, and the output of the NOT flop (or bit) would be a binary ONE, thereby specifying that when the data is not equal to 2, the trace flop 111 will be reset. To complete the initiation of the logic in FIG. 1 for the example being discussed, trace flop 111 must also be initially set by applying a binary ONE signal on line 110 which is an input to the set (S) input of trace flop 111 such that the output thereof, signal TR+ on line 112, will initially be a binary ONE.
Having established the initial trace conditions within the logic of FIG. 1, the execution of the software can be initiated or allowed to continue and the software analyzer can begin to function. During each memory operation, when the address of the memory location being accessed becomes available on lines 101, it is latched into execution address register 102 such that it will be continually available as signals EA+ on lines 103. With the execution address available on lines 103 at the A input of address comparator 107 and the trace address on lines 106 available at the B inputs of address comparator 107, the output thereof, signal EQA+, on line 108 will be a binary ONE if the execution address equals the trace address and a binary ZERO if the execution address does not equal the trace address.
At the appropriate moment during a memory operation, when the data being written into the addressed memory location, or the data being read from the addressed memory location, becomes available on lines 123, it is latched into execution address register 124 such that it is continuously available at the outputs thereof as signals ED+ on lines 125. Data comparator 132 compares the execution data on lines 125 at its A inputs with the trace data on lines 128 at its B inputs, masked with the trace data mask available on lines 131 at its X inputs. If each A input bit is equal to the corresponding B input bit has a binary ONE in the corresponding data mask bit at the X inputs, comparator 132 produces a binary ONE at its output as signal EQ+ on line 133. For each corresponding A and B input of data comparator 132 which has a binary ZERO in the corresponding data mask bit at its X inputs, the data comparator makes no comparison between the A and B input bits which are treated as "don't care" bits and therefore do not effect the output of comparator 132.
NOT multiplexer 136 is used to select between the output of data comparator 132 or the inverted output of data comparator 132 as a function of the binary value of the NOT bit from trace condition register 116 which appears as signal NC+ on line 119 at the select (S) input of multiplexer 136. If the NOT bit is a binary ZERO, NOT multiplexer 136 will gate signal EQ+ on line 133 at its 0 input onto its output as signal EQD+ on line 137. If the NOT bit in trace condition register 116 is a binary ONE, NOT multiplexer 136 will gate the inverted output of data comparator 132, signal NEQ+ on line 135, which is the output of inverter 134, at the 1 input of NOT multiplexer 136 onto its output as signal EQD+ on line 137. Thus, signal EQD+ on line 137 will be a binary ONE when the NOT bit of trace condition register is a binary ZERO and the execution data equals the trace data as masked according to the data mask. And it will also be a binary ONE when the execution data does not equal the trace data when the NOT bit is a binary ONE. Signal EQD+ on line 137 will be binary ZERO for all other conditions.
Both the equal address signal EQA+ on line 108 and the equal data signal EQD+ on line 137 are input into set AND gate 109 and reset AND gate 120. In addition, clocking signal CLK+ on line 122 is input to both AND gates 109 and 120. The fourth input to set AND gate 109 is the output of the set bit of trace condition register 116, signal SE+ on line 117. The fourth input of reset AND gate 120 is the output of the reset bit of trace condition register 116, signal RE+ on line 118.
Once each memory operation, at the appropriate moment, clocking signal CLK+ on line 122 transitions from the binary ZERO state to the binary ONE state thus partially enabling AND gates 109 and 120. At this time, the output of set AND gate 109, set flop signal SF+ on line 110 will become a binary ONE if the equal address signal EQA+ on line 108 is a binary ONE and the equal data signal EQD+ on line 137 is a binary ONE and the set bit in trace condition register 116 is a binary ONE. Alternatively, at this time, the output of reset AND gate 120, reset flop signal RF+ on line 121 will become a binary ONE is the equal address signal EQA+ on line 108 and the equal data signal EQD+ on line 137 are binary ONE's and the reset bit in trace condition register 116 is a binary ONE. If both the equal adress signal and the equal data signal on lines 108 and 137, respectively, are not both binary ONE's, or if neither the set bit nor the reset bit in trace condition register is a binary ONE, neither the set flop signal SF+ on line 110, nor the reset flop signal RF+ on line 121 will become a binary ONE.
As discussed previously, when the set flop signal on line 110 at the S input at the trace flop 111 becomes a binary ONE, the output of trace flop 111 signal TR+ on line 112 will become or remain a binary ONE. Conversely, if trace flop 111 is already set, the occurrence of a binary ONE at its reset (R) input by signal RF+ becoming a binary ONE on line 121 will cause trace flop 111 to reset and make the output thereof signal TR+ on line 112 a binary ZERO. Completing the above example, it can be appreciated that when the execution address register 102 contains a value of 100, and when execution data register 124 contains a value other than 2, the output of reset AND gate 120 will become a binary ONE and thus reset trace flop 111 making its output signal TR+ on line 112 a binary ZERO and inhibit the further tracing of the memory operations thereby saving in the trace memory all memory operations up to the point where the memory operation of interest occurred.
Although the prior art logic illustrated in FIG. 1 functions well to the extend that it allows one comparison to be performed per memory operation, there are cases in which it is desirable for a software analyzer to be able to perform more than one comparison per memory operation. Therefore, what is needed is a logic design which permits multiple compares to be made without exceeding the total elapsed time of a memory operation.